Forming a conductive structure in a semiconductor device

ABSTRACT

A conductive structure for use in a semiconductor device includes a multilayer structure. A first layer includes a material containing silicon, e.g., polysilicon and silicon germanide. A barrier layer is formed over the first layer, with the barrier layer including metal silicide or metal silicide nitride. A top conductive layer is formed over the barrier layer. The top conductive layer can include metal or metal silicide. Selective oxidation can be performed to reduce the amount of oxidation of selected materials in a structure containing multiple layers, such as the multilayer conductive structure. The selective oxidation is performed in a single-wafer rapid thermal processing system, in which a selected ambient, including hydrogen, is used to ensure low oxidation of a selected material, such as tungsten or a metal nitride.

[0001] This is a divisional of co-pending and commonly assigned U.S.patent application Ser. No. 09/031,407, entitled “Forming a ConductiveStructure in a Semiconductor Device,” filed Feb. 26, 1998.

BACKGROUND

[0002] The invention relates to forming a conductive structure in asemiconductor device.

[0003] Advanced integrated circuits in a semiconductor device requirehigh speed interconnecting lines between circuits for improved devicespeed. Interconnecting lines are typically made of metal, e.g.,aluminum, titanium. However, in some parts of a semiconductor device,particularly in regions where components are densely packed (such as thearray of a memory device), or in regions where further heat steps areneeded after formation of the interconnecting line during themanufacturing process, other materials are also widely used to forminterconnecting lines, e.g., doped polysilicon or N+ or P+ diffusedregions.

[0004] The different types of interconnecting lines exhibit differentresistivities, with metal generally having the lowest resistivity.Polysilicon, which is also typically used as the conductive electrode atthe gate of an N-channel or P-channel metal-oxide-silicon field effecttransistor (MOSFET), exhibits a higher resistivity than metal.

[0005] As the speed requirements of semiconductors increase, theresistance of interconnecting lines, especially those formed of a higherresistivity material (such as polysilicon) reduces switching speeds ofcircuits in the device. The resistance of a line increasesproportionately with its length. Thus, a polysilicon line running over along length and connected to a large capacitive load, such as a wordlinein a memory array connected to multiple transistors in the array, wouldcause a high RC delay during circuit switching.

[0006] One approach to reduce the resistivity of a polysiliconinterconnect line is to use a polycide structure, in which a lowresistance silicide (e.g., WSix) is formed on top of a doped polysiliconlayer. This effectively forms a two-layer interconnect line in which thesilicide layer provides a low resistivity conductive path.

[0007] Three-layer interconnecting lines have also been proposed,including a polymetal composite structure having tungsten (W) as the toplayer, tungsten silicide nitride (WSiN) as the intermediate layer, andpolysilicon as the bottom layer. The polymetal structure has aresistivity lower than the polycide structure that includes tungstensilicide on polysilicon.

SUMMARY

[0008] In general, according to one embodiment, a method of forming aconductive structure in a semiconductor device includes forming a lowerelectrically conductive layer on a support surface and forming anelectrically conductive barrier over the lower layer. Further, an upperconductive layer is formed over the barrier layer, the upper conductivelayer including metal silicide.

[0009] Other features and embodiments will become apparent from thefollowing description and from the claims.

BRIEF DESCRIPTION OF THE DRAWINGS

[0010]FIG. 1 is an enlarged, cross-sectional view of a transistor in asemiconductor device.

[0011]FIG. 2 is a flow diagram of the fabrication steps for formingportions of the transistor structure of FIG. 1.

[0012]FIGS. 3, 4, and 5 are block diagrams of single-wafer rapid thermalprocessing systems for performing selective oxidation.

[0013]FIG. 6 is graph of an X-ray photoelectron spectrometer (XPS)surface analysis showing the selective oxidation region for a multilayerconductive structure.

DETAILED DESCRIPTION

[0014] Referring to FIG. 1, a multilayer, low resistivity conductivestructure is described. The conductive structure can be used as part ofthe gate structure of a MOS transistor (as shown) or as aninterconnecting line to connect circuits, such as a wordline used toconnect transistors connected to memory cells in a memory array.

[0015] In FIG. 1, a transistor 12 is formed on a base 10, which includesa semiconductor (e.g., silicon) substrate or multilayer substrate (e.g.,silicon-on-insulator or SOI substrate). The transistor 12 is adjacent afield oxide layer 110. The transistor includes source and drain regions108A and 108B and a channel region 109. If the transistor 12 is used ina memory array, the source would be connected to a memory cell capacitorstructure (not shown), while the drain would be connected to a digitline (not shown). The transistor 12 can also have many other uses in asemiconductor device.

[0016] A gate oxide layer 106 is formed above the channel region 109. Agate stack 112 is then formed over the gate oxide layer 106. In oneembodiment, the gate structure 112 includes three electricallyconductive layers (100, 102, 104) to reduce the resistivity of the gate.The three-layer structure can also be used to form an interconnectingline separate from the transistor 12, in which case the gate oxide layer106 beneath the stack 112 would be replaced with other insulatinglayers.

[0017] The bottom conductive layer 104 is formed of a material thatincludes silicon, e.g., doped or undoped polysilicon, silicon germanium(SiGex), or amorphous silicon. The top conductive layer 100 includes alow resistivity material, which can be metal or metal silicide.Sandwiched between the top layer 100 and the bottom layer 104 is aconductive diffusion barrier layer 102 that is resistant to oxidation,agglomeration, and silicidation.

[0018] The barrier layer 102 acts to prevent agglomeration of siliconfrom the bottom layer 104 into the top conductive layer 100. Forexample, titanium silicide (TiSix) formed on polysilicon may result inagglomeration of silicon into the TiSix grains, which can increaseresistivity. Silicidation can also occur between certain top layer andbottom layer materials, such as tungsten (W) formed on polysilicon, inwhich formation of higher resistivity Wsix can occur.

[0019] The barrier layer 102 is formed of a material that includes metalsilicide, metal nitride, or metal silicide nitride, such as tungstensilicide (Wsix), tungsten silicide nitride (WSixNy), titanium silicidenitride (TiSixNy), tantalum silicide (TaSix), tantalum silicide nitride(TaSixNy), molybdenum silicide (MoSix), and molybdenum silicide nitride(MoSixNy), hafnium silicide (HfSix), hafnium silicide nitride (HfSixNy),zirconium silicide nitride (ZrSixNy), niobium silicide (NbSix), niobiumsilicide nitride (NbSixNy), and titanium nitride (TiNy).

[0020] Generally, a silicide, nitride, or silicide nitride compositionis resistant to oxidation and is stable at high temperatures. Theability to withstand high temperatures is particularly important sincethe gate structure or interconnecting line is put through varioussubsequent high temperature process steps, including source-drainimplant anneal, oxidation, and glass flow/reflow.

[0021] Metal silicides, nitrides, or silicide nitrides also have otherdesirable properties, including low resistivity, ease of formation,controlled oxidation properties, and stability in an oxidizing ambient.These materials also have excellent adhesion characteristics and exhibitlow stress contacts.

[0022] The resistivity of a metal silicide, metal nitride, or metalsilicide nitride barrier layer 102 is dependent on several factors,including the method of formation, annealing times and temperatures, andchemical purity. The stoichiometry of the refractory metal silicide,metal nitride, or metal silicide nitride composition can also affectresistivity; e.g., the x value of an MSix composition and the x and yvalues of an MSixNy composition can affect the resistivity.

[0023] In the barrier layer 102 containing an MSixNy composition, thevalue of x for silicon can be set at a value greater than 2, while thevalue of y for nitrogen is set in the range between about 0.1 and 0.9,preferably between about 0.5-0.6. With higher y values, the MSixNycompositions are more stable at higher temperatures, but thecompositions also have higher resistivities.

[0024] The top conductive layer 100 can be made from low resistivitymaterials, e.g., metal or metal suicides, such as tungsten (W), cobalt(Co), titanium silicide (TiSix), cobalt silicide (CoSix), nickelsilicide (NiSix), or other metal or metal silicide layers. Typically,the value of x may be greater than or equal to 2, with the exception ofNiSix, where x can be equal to one. Generally, the metal silicidecompositions are more stable at high temperatures than tungsten orcobalt, which tend to have relatively high oxidation rates.

[0025] The gate stack 112 and the gate oxide 106 are electricallyinsulated by side insulating spacers 114A and 114B and a top insulatinglayer 116. The insulating materials can be formed using silicon nitride(Si₃N₄) or silicon dioxide (SiO₂).

[0026] Referring to FIG. 2, the fabrication flow of portions of thetransistor 12 shown in FIG. 1 is illustrated. After the field oxide 110and source-drain regions 108A and 108B are formed in the base 10, thegate oxide 106 is formed on the surface of the base 10 (step 202) bythermal growth or deposition such as chemical vapor deposition (CVD).The thickness of the gate oxide 106, for current generationtechnologies, can typically range from about 30 angstroms (A) to 150 A.

[0027] Next, the bottom conductive layer 104 (which can includepolysilicon, SiGex, or amorphous silicon) is formed, such as bydeposition using a low pressure chemical vapor deposition (LPCVD)process. The bottom conductive layer 104 can have an exemplary thicknessranging from about 100 A to 3,000 A. The polysilicon, SiGex, oramorphous silicon layer 104 can also be doped with a dopant such asphosphorous or boron to improve electrical conductivity.

[0028] Next, the barrier layer 102 is formed (step 206) to a thicknessbetween about 50 A to 500 A, for example. Various methods can be used toform the diffusion barrier layer 102, including using chemical vapordeposition (CVD), physical vapor deposition (PVD), or depositionfollowed by a high temperature anneal of a metal (e.g., tungsten ortitanium) in an ambient containing nitrogen, ammonia (NH₃), or hydrazine(N₂H₄) in a rapid thermal processing (RTP) system.

[0029] Formation of metal silicide barrier layers using CVD may involvedeposition of the metal onto the bottom conductive layer 104 followed bysubsequent heating, which causes the metal and silicon containingmaterial in the layer 104 to react to form a silicide. This type ofsilicide formation can yield low resistivity silicide layers.

[0030] To form a barrier layer 102 having metal silicide nitride(MSixNy) or metal nitride (MNy), the metal deposition onto the bottomconductive layer step is followed by a high temperature (e.g., 600-1000°C.) anneal in an ambient including NH₃ or N₂H₄. The NH₃ or N₂H₄ annealcan be performed in a rapid thermal processing (RTP) system for apredetermined amount of time, e.g., between about 1-60 seconds. If themetal deposited is tungsten on a polysilicon, SiGex, or amorphoussilicon layer, the anneal step forms a barrier layer that contains Wsixand SiN, with no formation (or very little formation) of tungstennitride (WN), as illustrated by the X-ray photoelectron spectrometer(XPS) profile graph shown in FIG. 6. Wsix and SiN are more oxidationresistant than WN or tungsten. The high temperature anneal can also beperformed with a titanium on a silicon-containing material structure.The anneal in the NH₃ or N₂H₄ ambient forms a TiNy barrier layer.

[0031]FIG. 6 shows the percentage of materials present in aWsix-polysilicon stack after anneal of a W/poly-Si structure in an NH₃ambient at 750° C. The depth (as defined by an axis generally projectingperpendicularly from the surface of the base 10) begins at the topsurface (0 Å) of the stack 112 (without the top conductive layer 100)and continues downwardly into the stack. A layer of tungsten isinitially deposited on polysilicon. After anneal in the NH₃, the layersformed include a tungsten layer 100 at the top and a Wsixny barrierlayer 102 between the top tungsten layer and the bottom conductive layer104.

[0032] PVD by sputtering or evaporation can also be used to form metalsilicides and metal silicide nitrides. The evaporation method utilizessimultaneous deposition of the metal and silicon (or metal, silicon andnitrogen) under high vacuum or sputtering of a metal silicide compositetarget. Sputtering of the metal and silicon (or metal, Si, and N) can beperformed using RF or magnetron sputtering.

[0033] After formation of the barrier layer 102, the metal or metalsilicide conductive layer 100 is formed over the barrier layer 102 (step208), using either CVD or PVD techniques, for example. The conductivelayer 100 can be formed to a thickness between about 200 A to 2000 A.Following formation of the top conductive layer 100, the electricallyinsulating cap layer 116 is formed over the conductive layer 100 as anetch stop and oxidation barrier (step 210). The insulating layer 116 canbe formed using vapor deposited SiO₂ or Si₃N₄. A dry etch process (suchas reactive ion etching) is then used to form the gate stack (step 212).

[0034] After the gate stack is formed, nitride insulating spacers 114Aand 114B can optionally be formed using known methods, such as by LPCVDor PECVD nitride (step 214). Oxide spacers can also be used, such asthose formed using CVD with tetraethylorthosilicate (TEOS). Whether thisstep is performed depends on the type of materials used in forming thestack 112.

[0035] For example, if a stack having a tungsten conductor on a titaniumnitride barrier is used, then the spacers are useful as etch barriers aswell as oxidation barriers in subsequent processing steps. The spacers116A and 116B may also be used with other stacks that contain a metalconductor on a metal silicide or nitride barrier.

[0036] The spacer forming step 214 may not be needed when a stack havinga metal silicide conductor on a metal silicide or metal silicide nitridebarrier (e.g., TiSix conductor on Wsix barrier) is used. With suchstacks, the spacer formation is performed after the source-drainre-oxidation step (216).

[0037] The source-drain re-oxidation step (216) is performed to removedamage caused by reactive ion etching and patterning of the gateelectrode. The re-oxidation step causes oxide to be thermally grown onthe sidewall of the etched polysilicon, SiGex, or amorphous siliconelectrode, which also serves to thicken the gate oxide 106 at the gateedge to improve the gate oxide dielectric strength. The source-drainre-oxidation can be performed in the following environment: O₂; O₂/H₂;N₂O; NO; or a selective ambient, such as an H₂O/H₂ ambient in which theratio of H₂O to H₂ is controlled to predetermined ranges.

[0038] If the top conductive layer 100 is formed of a metal silicidematerial, and the barrier layer 102 is formed of a metal silicide ormetal silicide nitride material, then the two layers are relativelyresistant to oxidation and any of the source-drain re-oxidationtechniques listed above can be used. However, certain materials that canbe used in the top conduction layer 100, such as tungsten (W) ortitanium (Ti), and certain materials in the barrier layer 102, such as ametal nitride (e.g., TiN), have relatively high oxidation rates.

[0039] For example, tungsten oxidation rate is much faster than that ofsilicon, and typical oxidation processes can cause the volume oftungsten oxide (WO₃) to be much larger than that of W. If WO₃ formationoccurs, peeling or morphological degradation of the tungsten film mayoccur. Thus, in cases where the top conduction layer 100 has arelatively high oxidation rate, a selective oxidation process ispreferred over conventional oxidation or wet oxidation. Similar issuesexist when titanium is used as the top conduction layer 100.

[0040] Possible metal nitride materials (in addition to the materialsdiscussed above) for the barrier layer 102 include tungsten nitride (WN)or titanium nitride (TiN), which are susceptible to relatively fastoxidation. If such barrier layers are used, then selective oxidation maybe particularly advantageous. However, even if metal silicide topconductive layers 100 or metal silicide or metal silicide nitridebarrier layers 102 are used, the selective oxidation process may alsohelp to reduce the rate of oxidation of those materials.

[0041] Selective source drain re-oxidation can be performed in a watervapor ambient with controlled amounts of hydrogen added in asingle-wafer rapid thermal processing (RTP) system (e.g., an AG8108 HeatPulse RTP system) for selective oxidation of silicon over the metal,metal silicide, metal silicide nitride, or metal nitride top conductinglayer 100 or barrier layer 102. In addition, use of a single-wafersystem, such as the three types shown in FIGS. 3-5, provide severaladvantages over use of a furnace that can receive multiple wafers. In asingle-wafer RTP system, better control of process conditions can beachieved. For example, better uniformity of temperature can be achievedover the entire surface of the wafer, which is particularly advantageouswhen large wafers (e.g., 300 mm wafers) are used. In addition, betterambient control and uniformity of oxidation over the entire processedsurface of a wafer can be achieved.

[0042] The described selective oxidation processes (shown in FIGS. 3, 4,and 5) can also be applied to multi-wafer furnace systems.

[0043] Referring to FIG. 3, an RTP single-wafer system uses an ambientof argon-hydrogen (Ar—H₂) and water vapor. Other inert gases besides Arcan also be used. By controlling the ratio of H₂O to O₂, use of thisambient can reduce oxidation of a metal (e.g., tungsten) top conductivelayer 100 and WN, Wsixny, TiN, and other metal nitride conductivediffusion barrier layers 102.

[0044] A quartz vessel 300 (which can contain 20 liters of liquid) isfilled approximately half full of deionized water through a liquid flowcontroller 304 from a source 306. The vessel 300 is then heated andmaintained at an elevated temperature, e.g., between about 95-98° C.,through use of an external heating blanket 314 affixed to the outside ofthe quartz vessel 300. The elevated temperature evaporates portions ofthe deionized water.

[0045] The temperature of the deionized water in the vessel 300 ismonitored by a thermocouple 308 inserted into a sheath in the quartzvessel 300. The over temperature trip level of the thermocouple 308 canbe set at about 120° C. The thermocouple 308 is connected to atemperature and water level controller 310 for monitoring. Thecontroller 310 adjusts the temperature of the blanket 314 as the liquidtemperature in the vessel 300 varies. Over temperature thermocouples(not shown) can also monitor the heater blanket 314 temperature toprevent heater blanket temperature runaway.

[0046] The level of the deionized water in the vessel 300 is monitoredby a liquid level sensor 312, also connected to the controller 310. Thecontroller 310 adjusts the flow rate through the flow controller 304 tomaintain the level of the liquid in the vessel 300. The autofill featurefor the deionized water is disabled during a process run (to perform thesource drain re-oxidation) so as not to disturb the water vapordelivery.

[0047] Delivery of the deionized water vapor is achieved by injecting anAr—H₂ mixture into the vessel 300 through a mass flow controller 322 ata predetermined rate. The Ar—H₂ comes from a source 318. The H₂ canoriginate from a pure hydrogen source or from a breakdown of a hydrogencontaining compound such as NH₃ or N₂H₄. The resulting water and argonvapor is transported through a line 316 (which can be a {fraction (1/2)}inch heat taped stainless steel line) maintained at a predeterminedtemperature, e.g., about 110° C., to prevent recondensation of thevapor.

[0048] The vapor in the line 316 flows through a vapor flow controller324 to a single-wafer process chamber 302. Other conventional RTPprocess gases are also provided through flow controllers 326 to theprocessor chamber 302. The flow of H₂O can be selected to be in therange between about 1 SCCM (standard cubic centimeters per minute) and50 SLM (standard liters per minute), with a preferred range of about 1SCCM to 10 SLM. The flow rate of H₂ can be selected to a value in therange between about 1 SCCM and 50 SLM, with a preferred range of about 1SCCM to 20 SLM. In the AG8108 system, the H₂O/H₂ partial pressure ratiocan be maintained between about 2.3 and 2.8. However, the ratios varyaccording to the specific types of RTP systems used. The processingtemperature in the single-wafer processing chamber can be maintainedbetween about 950° C. and 1100° C. Selective oxidation of silicon overtungsten of about 2:1 can be achieved using the system of FIG. 3.

[0049] Referring to FIG. 4, an alternative single-wafer RTP systemperforms source-drain selective re-oxidation using a different transportsystem. Elements that are the same as in the RTP system of FIG. 1 havecommon reference numerals. As in the RTP system of FIG. 1, apredetermined amount of deionized water is kept in the vessel 300 (e.g.,half full in a 20-liter vessel). However, delivery of the deionizedwater vapor is achieved through the use of a vapor flow controller 330,rather than through use of the mass flow controller 322 to pump argon318 into the vessel 300 to move vapor through the line 316. The pressurein the water vessel 300 can be approximately 960 Torr, which issufficient to generate ample flow through the vapor flow controller 330.The vapor is then transported through the line 316 to the processchamber 302, with the line temperature maintained at about 110° C. toprevent recondensation of the vapor. Hydrogen is passed through one ofthe vapor flow controllers 326 to the process chamber 302 to performselective oxidation of silicon over other materials.

[0050] Referring to FIG. 5, an RTP system with an external torchassembly is used to create the water vapor flow for selective oxidation.Hydrogen (H₂) and oxygen (O₂) are delivered through vapor flowcontrollers 350 and 352, respectively, from sources 354 and 356,respectively. The H₂ and O₂ are delivered to an injector 360 insertedinto the external torch assembly 358. The torch assembly 358 ismaintained at a temperature of about 900° C. to provide ignition energy.The resulting water vapor and H₂ mixture is delivered to thesingle-wafer process chamber 302 via a quartz tube interface 362.

[0051] As is the case with the RTP system of FIG. 3, the RTP systems ofFIGS. 4 and 5 also maintain a predetermined H₂O/H₂ partial pressureratio and temperature.

[0052] In the RTP system of FIG. 5, safety measures are provided by anexternal controller 364, which monitors and maintains the external torchelement temperature and provides over temperature and runaway safeties.The controller 364 can also implement steps to ensure safety associatedwith using H₂ as a process gas. The safety mechanisms implementedinclude maintaining a particular H₂/O₂ ratio. Thus, H₂ flow is disabledif no O₂ is present; H₂ is disabled if the torch temperature is below700° C.; an initial nitrogen (N₂) purge is performed of the injector 360before the flow of H₂ is turned on; and H₂ leak detectors are used todetermine when to turn off and purge the H₂ line if an H₂ leak isdetected. The controller 364 also monitors the temperature of theprocess chamber 302 to prevent water vapor from being formed if theprocess chamber 302 is below 700° C. to prevent recondensation of thewater vapor.

[0053] Other embodiments are also within the scope of the followingclaims. Although the layers in the multilayer conductive structure havebeen described with certain thicknesses for each layer, it iscontemplated that the layer thicknesses can be varied and still achievedesirable results. The conductive structure described can be formed witha stack having more than three layers. Further, various systems andprocesses have been described with particular parameters; theseparameters can also be varied. The systems described have componentsassociated with certain, specific parameters and values, which can bevaried.

What is claimed is:
 1. A method of forming a multi-layer conductivestructure in a semiconductor device, the method comprising: forming afirst layer containing silicon; depositing a metal layer over the firstlayer; and annealing the metal layer in an ambient having a compositionselected from a group consisting of nitrogen, NH₃, and hydrazine,wherein a second layer containing silicide is formed over the firstlayer after annealing.
 2. The method of claim 1 , wherein the secondlayer contains a metal silicide nitride composition.
 3. The method ofclaim 1 , further comprising forming a top conductive layer over thesecond layer.
 4. The method of claim 3 , wherein the first layer, secondlayer, and top conductive layer form the multi-layer conductivestructure.
 5. A method of forming a conductive structure in asemiconductor device, the method comprising: forming a lowerelectrically conductive layer on a support surface; forming anelectrically conductive barrier layer over the lower layer; and formingan upper conductive layer over the barrier layer, the upper conductivelayer including metal silicide.
 6. The method of claim 5 , wherein thelower layer includes silicon.
 7. The method of claim 5 , wherein thelower layer includes a material selected from the group consisting ofpolysilicon, SiGex, and amorphous silicon.
 8. The method of claim 5 ,wherein the barrier layer includes a metal silicide composition.
 9. Themethod of claim 5 , wherein the barrier layer includes a metal silicidenitride composition.
 10. The method of claim 5 , wherein the upperconductive layer includes a material selected from the group consistingof TiSix, CoSix, NiSix, and PdSix.
 11. A method of forming a conductivestructure in a semiconductor device, comprising: forming a firstelectrically conductive layer on a base; forming a barrier layer overthe first layer, the barrier layer including a metal silicide; andforming a second electrically conductive layer over the barrier layer.12. The method of claim 11 , wherein the barrier layer includes tungstensilicide.
 13. The method of claim 11 , wherein forming the barrier layerincludes using chemical vapor deposition.
 14. The method of claim 11 ,wherein forming the barrier layer includes using physical vapordeposition.
 15. The method of claim 11 , wherein forming the barrierlayer includes depositing a metal on a layer containing silicon andcontrolling the metal-silicon structure in a preselected ambient. 16.The method of claim 15 , wherein the preselected ambient includes NH₃.17. The method of claim 15 , wherein the preselected ambient includeshydrazine.
 18. The method of claim 15 , wherein the preselected ambientincludes nitrogen.
 19. A method of oxidizing layers formed on a base ofa semiconductor device, the layers including a first layer containingsilicon, the method comprising: generating a predetermined mixture of H₂and H₂O; providing the mixture to a single-wafer thermal processingchamber; and heating the chamber to selectively oxidize the first layerover one or more other layers.
 20. The method of claim 19 , furthercomprising: generating a flow of a mixture containing H₂O vapor and H₂by injecting an inert gas.
 21. The method of claim 20 , wherein theinert gas includes Argon.
 22. The method of claim 19 , furthercomprising: filling a vessel with deionized water; and heating thevessel to evaporate a portion of the water.
 23. The method of claim 22 ,wherein injecting the inert gas includes injecting the inert gas intothe vessel.
 24. The method of claim 19 , wherein heating the processingchamber includes heating the processing chamber to a temperature betweenabout 950° C. and 1100° C.
 25. The method of claim 19 , whereingenerating the mixture of H₂ and H₂O includes injecting H₂ and O₂ vaporinto a heating element.
 26. The method of claim 25 , wherein the heatingelement includes a torch heater assembly.
 27. The method of claim 26 ,further comprising maintaining the torch heater assembly at atemperature above about 900° C. to provide ignition energy.
 28. Themethod of claim 19 , wherein the one or more other layers includetungsten.
 29. The method of claim 19 , wherein the one or more otherlayers include a metal nitride.
 30. The method of claim 34 , wherein theone or more other layers include a stack containing second and thirdlayers formed over the first layer, the second and third layers bothbeing electrically conductive.
 31. An oxidation system for oxidizinglayers formed on a base of a semiconductor device, a first layercontaining silicon, the oxidation system comprising: a source of H₂vapor; a source of H₂O vapor; a flow controller connected to deliver amixture of H₂O and H₂; and a process chamber in which the semiconductordevice is placed, the process chamber connected to receive the mixtureof H₂O and H₂ to perform selective oxidation of the first layer over theother layers.
 32. The system of claim 31 , wherein the source of H₂Ovapor includes a vessel containing water heated to evaporate a portionof the water.
 33. The system of claim 32 , wherein the inert gas isinjected into the vessel.
 34. The system of claim 32 , wherein the H₂vapor is injected with the inert gas.
 35. The system of claim 31 ,wherein the H₂O/H₂ mixture has a partial pressure ratio of between about2.3 and 2.8.
 36. The system of claim 35 , wherein the process chamber isheated to a temperature between about 950° C. and 1100° C.
 37. Thesystem of claim 31 , wherein the process chamber is a single-waferprocess chamber.
 38. The method of claim 31 , wherein the other layersinclude tungsten.
 39. The method of claim 31 , wherein the other layersinclude a metal nitride.
 40. A selective oxidation system for oxidizinglayers formed on a base of a semiconductor device, a first layercontaining silicon, the system comprising: a source of H₂ vapor; asource of O₂ vapor; a heating element connected to receive H₂ vapor andO₂ vapor, the heating element being heated to generate a mixture of H₂Oand H₂ having a predetermined partial pressure ratio; and a processchamber in which the semiconductor device is place, the process chamberconnected to receive the mixture of H₂O and H₂ to perform selectiveoxidation of the first layer over the other layers.
 41. The system ofclaim 40 , wherein the heating element is heated to above apredetermined temperature to generate H₂O vapor.
 42. The system of claim40 , wherein the heating element includes a torch heater assembly. 43.The system of claim 42 , wherein the torch heater assembly is maintainedat a temperature above about 700° C. to provide ignition energy.